Bât. Breguet C4.21
3 rue Joliot Curie
91190 Gif-sur-Yvette, France
From the algorithm to the targets, optimisation flow for the real-time high performance computing on heterogeneous parallel embedded system
Thales TRT and the L2S laboratory are both tackling, in different contexts, the subject of finding optimal performance in an environment where algorithms and computing architectures tend to become more complex.
The path towards better performance for embedded applications (spatial, defence, security, public transportation…) requires the conjunction of different skillsets, often split across different teams if not different business entities. Indeed, on the one hand, applications are becoming more and more demanding in terms of computing power, and on the other hand, embedded systems require an increasingly sophisticated use of their computing resources due in particular to a heterogeneity of targets (CPU, GPU, DSP, FPGA…) and complex data communication links.
In this search for the best combination of architectures and algorithms to meet the particularly strong constraints in the field of embedded systems (real time, low energy consumption, controlled cost and of course the accuracy of the results), the frontier between expertise in the field of application and expertise in embedded systems is becoming increasingly marked.However, it reduces the space for exploring solutions likely to best optimize the application on a hardware target and can potentially prevent the achievement of the expected performances.
In this context, more in-depth optimization work at the interface between the application and embedded high-performance computing is proving to be more than necessary.
An efficiency-driven approach for real-time optical flow processing on parallel hardware
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